Fabricating process of circuit substrate and circuit substrate structure

ABSTRACT

A fabricating process of circuit substrate sequently includes: providing a substrate with a pad and a dielectric stack layer disposed at the substrate and overlaying the pad, in which the stack layer includes two dielectric layers and a third dielectric layer located between the two dielectric layers, and the etching rate of the third dielectric layer is greater than the etching rate of the two dielectric layers; forming an opening corresponding to the pad at the stack layer; performing a wet etching process on the stack layer to remove the portion of the third dielectric layer surrounding the opening to form a gap between the portions of the two dielectric layers surrounding the opening; performing a plating process on the stack layer and the pad to respectively form two plating layers at the stack layer and the pad, in which the gap isolates the two plating layers from each other.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 99125377, filed Jul. 30, 2010. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention generally relates to a circuit substrate structure and a fabricating process of circuit substrate, and more particularly, to a circuit substrate structure with an active surface having a metallic plating layer and a fabricating process thereof. The structure and the method of the invention are suitable for a semiconductor substrate with miniaturized electronic devices already made and a semiconductor substrate without other miniaturized electronic devices and meanwhile can be further applicable in fabricating a reflective layer disposed on a ceramic substrate with a circuit and a metallic substrate with a circuit.

2. Description of Related Art

Along with the progress of semiconductor technology, a light-emitting diode (LED) has larger and larger power, and the intensity of the emitted light thereof becomes higher and higher. In addition, LEDs have advantages, such as power-saving, long lifetime, environment-friendly, fast starting, small size and so on, so that LEDs are widely applied in illumination equipment, traffic sign light, display, optical mouse and the like and would gradually substitute traditional fluorescent lamps.

In an LED package structure, there are an LED unit and a control unit, in which the control unit has pads thereon for electrically connecting the LEDs. In order to effectively reflect the light emitted from the LED unit to advance light-emitting efficiency, a reflective layer can be employed and disposed in the LED package structure, so that the light emitted from the LED unit can be effectively reflected by the reflective layer to advance light-emitting efficiency.

For example, a reflective layer made of silver (Ag) has the best effect, in which the control unit can be coated with silver thereon by plating, evaporation or vacuum sputtering. Plating silver is not a standard semiconductor process and has a practical difficulty when mass producing semiconductor substrates, while when making evaporation or vacuum sputtering to plate a reflective layer on the control unit, each pad may contact the reflective layer to electrically connect each other to result in an unexpected electrical connection, which would affect the normal operation of the LED unit. As a result, when a semiconductor device and a reflective layer are integrated into a single chip, how to avoid the reflective layer plated on a control unit and fabricated by evaporation or vacuum sputtering to contact pads becomes an important project in fabricating an LED package structure.

SUMMARY OF THE INVENTION

Accordingly, the invention is directed to a fabricating process of circuit substrate, in which the fabricated circuit substrate structure is able to avoid an unexpected electrical connection between each pad thereof and the rest pads through a connection between the plating layers.

The invention is also directed to a circuit substrate structure, which is able to avoid an unexpected electrical connection between each pad thereof and the rest pads through a connection between the plating layers.

The invention provides a fabricating process of circuit substrate. First, a substrate and a dielectric stack layer are provided, in which the substrate has a pad, the dielectric stack layer is disposed on the substrate and overlays the pad, the dielectric stack layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer located between the first dielectric layer and the second dielectric layer, and the etching rate of the third dielectric layer is greater than the etching rate of the first dielectric layer and the second dielectric layer. Next, an opening is formed at the dielectric stack layer, in which the opening is corresponding to the pad. Then, a wet etching process is performed on the dielectric stack layer to remove the portion of the third dielectric layer surrounding the opening so as to form a gap between the portion of the first dielectric layer surrounding the opening and the portion of the second dielectric layer surrounding the opening. Finally, a plating process is performed on the dielectric stack layer and the pad to respectively form a first plating layer and a second plating layer at the dielectric stack layer and the pad, in which the gap isolates the first plating layer from the second plating layer.

In an embodiment of the invention, the material of the above-mentioned dielectric stack layer includes silicon oxide (SiO₂) or silicon nitride (Si₃N₄).

In an embodiment of the invention, the material of the above-mentioned first dielectric layer and the second dielectric layer includes silicon oxide produced through a reaction by using tetraethylorthosilicate (TEOS) and the material of the third dielectric layer includes borophosphosilicate glass (BPSG).

In an embodiment of the invention, the above-mentioned method of performing the wet etching process on the dielectric stack layer is to perform wet etching with hydrogen fluoride (HF) solution on the dielectric stack layer.

In an embodiment of the invention, the above-mentioned fabricating process of circuit substrate further includes prior to performing the plating process, removing a portion of the dielectric stack layer to expose the pad.

In an embodiment of the invention, the above-mentioned method of removing a part of the dielectric stack layer includes plasma etching.

In an embodiment of the invention, the above-mentioned plating process is evaporation or sputtering.

In an embodiment of the invention, the above-mentioned fabricating process of circuit substrate further includes: forming a patterned recess at the dielectric stack layer; increasing the thickness of the dielectric stack layer to overlay the patterned recess, in which after removing the portion of the third dielectric layer surrounding the opening by using the wet etching process, the dielectric stack layer forms a saw-teeth shape structure at the place of the gap.

In an embodiment of the invention, the above-mentioned fabricating process of circuit substrate further includes: forming a dielectric material filling the patterned recess, in which the etching rate of the dielectric material is greater than the etching rate of the first dielectric layer and the second dielectric layer; at the same time as performing the wet etching process to remove the portion of the third dielectric layer surrounding the opening, removing the dielectric material by using the wet etching process so that the dielectric stack layer has a saw-teeth shape structure at the place of the gap.

The invention provides a circuit substrate structure, which includes a substrate, a dielectric stack layer, a first plating layer and a second plating layer. The substrate has a pad. The dielectric stack layer is disposed on the substrate and has an opening exposing the pad, in which the dielectric stack layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer located between the first dielectric layer and the second dielectric layer, and there is a gap between the portion of the first dielectric layer surrounding the opening and the portion of the second dielectric layer surrounding the opening. The first plating layer is disposed at the dielectric stack layer and the second plating layer is disposed at the pad, in which the gap isolates the first plating layer from the second plating layer.

In an embodiment of the invention, the material of the above-mentioned dielectric stack layer includes silicon oxide (SiO₂) or silicon nitride (Si₃N₄).

In an embodiment of the invention, the material of the above-mentioned first dielectric layer and the second dielectric layer includes silicon oxide produced through a reaction by using tetraethylorthosilicate (TEOS) and the material of the third dielectric layer includes borophosphosilicate glass (BPSG).

In an embodiment of the invention, the material of the above-mentioned first dielectric layer and the second dielectric layer includes silver (Ag).

In an embodiment of the invention, the above-mentioned dielectric stack layer has a saw-teeth shape structure at the place of the gap.

Based on the depiction above, in the circuit substrate structure of the invention, there is a gap between the portion of the first dielectric layer surrounding the opening and the portion of the second dielectric layer surrounding the opening. In this way, during performing a plating process on the dielectric stack layer and the pad, the gap has isolation function, so that a first plating layer and a second plating layer without contacting the first plating layer are respectively formed at the dielectric stack layer and the pad, which avoids an unexpected electrical connection between each pad thereof and the rest pads through the connection between the plating layers to ensure the normal operation of the circuit substrate.

The structure and the method of the invention are suitable for a semiconductor substrate with miniaturized electronic devices made already and a semiconductor substrate without other miniaturized electronic devices and meanwhile can be further applicable in fabricating a reflective layer disposed on a ceramic substrate with a circuit and a metallic substrate with a circuit.

Other objectives, features and advantages of the invention will be further understood from the further technological features disclosed by the embodiments of the invention in which there are shown and described preferred embodiments of this invention, simply by way of illustration of modes best suited to carry out the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIGS. 1A-1E are schematic flowcharts showing a fabricating process of circuit substrate according to an embodiment of the invention.

FIGS. 2A-2E are schematic flowcharts showing a fabricating process of circuit substrate according to another embodiment of the invention.

FIG. 3 is a top view diagram of the dielectric stack layer of FIG. 2A.

DESCRIPTION OF THE EMBODIMENTS

The structure and the method provided by the invention are suitable for a semiconductor substrate with miniaturized electronic devices made already and a semiconductor substrate without other micro electronic devices and meanwhile can be further applicable in fabricating a reflective layer disposed on a ceramic substrate with a circuit and a metallic substrate with a circuit.

FIGS. 1A-1E are schematic flowcharts showing a fabricating process of circuit substrate according to an embodiment of the invention, in which the process is a semiconductor process as an example. Referring to FIG. 1A, first, a substrate 110 and a dielectric stack layer 120 are provided, in which the substrate 110 has a pad 112, the dielectric stack layer 120 is disposed on the substrate 110 and overlays the pad 112, and the dielectric stack layer 120 includes a first dielectric layer 122, a second dielectric layer 124 and a third dielectric layer 126 located between the first dielectric layer 122 and the second dielectric layer 124. In the embodiment, the second dielectric layer 124, the third dielectric layer 126 and the first dielectric layer 122 are sequently deposed on the substrate 110 by using chemical vapor deposition (CVD) method.

In the embodiment, the material of the dielectric stack layer 120 includes silicon oxide. In more details, the material of the first dielectric layer 122 and the second dielectric layer 124 is, for example, silicon oxide produced through a reaction in vacuum plasma by using tetraethylorthosilicate (TEOS) and the material of the third dielectric layer 126 is, for example, silicon glass doped with boron-phosphor (BP), so that the etching rate of the third dielectric layer 126 is greater than the etching rate of the first dielectric layer 122 and the second dielectric layer 124, which the invention is not limited to. In other embodiments, the material of the dielectric stack layer 120 can be silicon nitride or a combo structure formed by stacking silicon oxide and silicon nitride as well, and also can be that by doping an appropriate substance into the first dielectric layer 122, the second dielectric layer 124 and the third dielectric layer 126 so that the etching rate of the third dielectric layer 126 is greater than the etching rate of the first dielectric layer 122 and the second dielectric layer 124.

Next, referring to FIG. 1B, an opening 120 a is formed at the dielectric stack layer 120, in which the opening 120 a is corresponding to the pad 112. The method to form the opening 120 a is, for example, a photomask process. In more details, a patterned photomask is formed on the dielectric stack layer 120, followed by removing the portion of the dielectric stack layer 120 exposed by the patterned photomask to form the opening 120 a.

Then, referring to FIG. 1C, a wet etching process is performed on the dielectric stack layer 120 to remove the portion of the third dielectric layer 126 surrounding the opening 120 a so as to form a gap G between the portion of the first dielectric layer 122 surrounding the opening 120 a and the portion of the second dielectric layer 124 surrounding the opening 120 a. In more details, for example, hydrogen fluoride (HF) solution is used to serve as an etching liquid to perform a wet etching process on the dielectric stack layer 120. Since the etching rate of the third dielectric layer 126 is greater than the etching rate of the first dielectric layer 122 and the second dielectric layer 124, the etched extent of the third dielectric layer 126 is larger than the etched extents of the first dielectric layer 122 and the second dielectric layer 124, and a gap G as shown by FIG. 1C is formed.

Referring to FIG. 1D, a portion of the dielectric stack layer 120 is removed to expose the pad 112, in which the method of removing the portion of the dielectric stack layer 120 is, for example, plasma etching. Then, referring to FIG. 1E, a plating process is performed on the dielectric stack layer 120 and the pad 112 to respectively form a first plating layer 120 b and a second plating layer 112 a at the dielectric stack layer 120 and the pad 112 to finish the fabrication of the circuit substrate structure 100. The plating process is, for example, evaporation or sputtering.

Since there is a gap G between the portion of the first dielectric layer 122 surrounding the opening 120 a and the portion of the second dielectric layer 124 surrounding the opening 120 a, during forming the first plating layer 120 b and the second plating layer 112 a through a plating process, the first plating layer 120 b formed at the dielectric stack layer 120 and the second plating layer 112 a formed at the pad 112 are isolated by the gap G and separated from each other.

The circuit substrate structure 100 of FIG. 1E includes a substrate 110, a dielectric stack layer 120, a first plating layer 120 b and a second plating layer 112 a. The substrate 110 has a pad 112, the dielectric stack layer 120 is disposed on the substrate 110 and has an opening 120 to expose the pad 112, in which the dielectric stack layer 120 includes a first dielectric layer 122, a second dielectric layer 124 and a third dielectric layer 126 located between the first dielectric layer 122 and the second dielectric layer 124. There is a gap G between the portion of the first dielectric layer 122 surrounding the opening 120 and the portion of the second dielectric layer 124 surrounding the opening 120. The first plating layer 120 b is disposed at the dielectric stack layer 120 and the second plating layer 112 a is disposed at the pad 112, in which the gap G isolates the first plating layer 120 b from the second plating layer 112 a. As a result, the invention can be able to avoid an unexpected electrical connection between each pad 112 thereof and the rest pads through the connection between the first plating layer 120 b and the second plating layer 112 a and thereby the normal operation of the circuit substrate structure is ensured.

In the circuit substrate structure 100 of the embodiment, the material of the first dielectric layer 122 and the second dielectric layer 124 is, for example, silicon oxide produced through a reaction in vacuum plasma by using tetraethylorthosilicate (TEOS) and the material of the third dielectric layer 126 is, for example, silicon glass doped with boron-phosphor (BP) or other kinds of silicon oxide. In addition, the material of the first plating layer 120 b and the second plating layer 112 a is, for example, silver. As an example, the circuit substrate structure 100 can be the substrate in an LED package structure and both the first plating layer 120 b and the second plating layer 112 a can be reflective layers in the LED package structure for reflecting the light emitted from the LED unit.

FIGS. 2A-2E are schematic flowcharts showing a fabricating process of circuit substrate according to another embodiment of the invention and FIG. 3 is a top view diagram of the dielectric stack layer of FIG. 2A. Referring to FIGS. 2A and 3, after forming the structure shown by FIG. 1B, a patterned recess 120 c is formed at the dielectric stack layer 120. Then in FIG. 2B, a portion of the dielectric stack layer 120 is removed to expose the pad 112 and a dielectric material 130 filling the patterned recess 120 c is formed, in which the etching rate of the dielectric material 130 is greater than the etching rate of the first dielectric layer 122 and the second dielectric layer 124. The material of the dielectric material 130 is the same as, for example, the material of the third dielectric layer 126. The material of the dielectric material 130 and the third dielectric layer 126 is, for example, silicon glass doped with boron-phosphor (BP).

Referring to FIG. 2C, the dielectric material 130 is overlapped by increasing the thickness of the dielectric stack layer 120. In more details, the method of increasing the thickness of the dielectric stack layer 120 is, for example, to dispose a dielectric layer with the same material as the material of the first dielectric layer 122 on the first dielectric layer 122. Referring to FIG. 2D, during performing a wet etching process, parts of the third dielectric layer 126 and the dielectric material 130 are removed so that the dielectric stack layer 120 has a saw-teeth shape structure at the place of the gap G. As shown by FIG. 2E, when a plating process is performed on the dielectric stack layer 120 and the pad 112 to respectively form the first plating layer 120 b and the second plating layer 112 a, it can further avoid the first plating layer 120 b and the second plating layer 112 a from extending along the inner-wall of the gap G and from contacting each other.

When the recess 120 c is quite small, the dielectric material 130 is not needed to fill the patterned recess 120 c. Instead, the thickness of the dielectric stack layer 120 should be directly increased and the gap G should at the original position of the recess 120 c should be kept. In this way, during forming the gap G, there is also a saw-teeth shape structure formed at the place of the gap G.

A circuit substrate structure 100′ shown by FIG. 2E includes a substrate 110, a dielectric stack layer 120, a first plating layer 120 b and a second plating layer 112 a. The substrate 110 has a pad 112, the dielectric stack layer 120 is disposed on the substrate 110 and has an opening 120 to expose the pad 112, in which the dielectric stack layer 120 includes a first dielectric layer 122, a second dielectric layer 124 and a third dielectric layer 126 located between the first dielectric layer 122 and the second dielectric layer 124. There is a gap G between the portion of the first dielectric layer 122 surrounding the opening 120 and the portion of the second dielectric layer 124 surrounding the opening 120 and the dielectric stack layer 120 has a saw-teeth shape structure at the place of the gap G. The first plating layer 120 b is disposed at the dielectric stack layer 120 and the second plating layer 112 a is disposed at the pad 112, in which the gap G and the saw-teeth shape structure isolate the first plating layer 120 b from the second plating layer 112 a. As a result, the invention can be able to avoid an unexpected electrical connection between each pad 112 thereof and the rest pads through the connection between the first plating layer 120 b and the second plating layer 112 a and thereby the normal operation of the circuit substrate structure is ensured.

In the circuit substrate structure 100′ of the embodiment, the material of the first dielectric layer 122 and the second dielectric layer 124 is, for example, silicon oxide or silicon nitride produced through a reaction in vacuum plasma and the material of the third dielectric layer 126 is, for example, silicon glass doped with boron-phosphor (BP) or other kinds of silicon oxide. In addition, the material of the first plating layer 120 b and the second plating layer 112 a is, for example, silver. As an example, the circuit substrate structure 100′ can be applied in an LED package structure and both the first plating layer 120 b and the second plating layer 112 a can be reflective layers in the LED package structure for reflecting the light emitted from an LED unit.

In summary, in a circuit substrate structure of the invention, there is a gap between the portion of the first dielectric layer surrounding the opening and the portion of the second dielectric layer surrounding the opening. In this way, during performing a plating process on the dielectric stack layer and the pad, the gap has isolation function, so that a first plating layer and a second plating layer without contacting the first plating layer are respectively formed at the dielectric stack layer and the pad, which avoids an unexpected electrical connection between each pad thereof and the rest pads through the connection between the plating layers to ensure the normal operation of the circuit substrate. In addition, the dielectric stack layer could have a saw-teeth shape structure at the place of the gap, such that the plating layer on the dielectric stack layer is further prevented from electrically connecting to the pad along a inner wall of the gap.

The structure and the method of the invention are suitable for a semiconductor substrate with miniaturized electronic devices made already and a semiconductor substrate without other miniaturized electronic devices and meanwhile can be further applicable in fabricating a reflective layer disposed on a ceramic substrate with a circuit and a metallic substrate with a circuit.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the invention covers modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents. 

What is claimed is:
 1. A fabricating process of circuit substrate, comprising: providing a substrate and a dielectric stack layer, wherein the substrate has a pad, the dielectric stack layer is disposed on the substrate and overlays the pad, the dielectric stack layer comprises a first dielectric layer, a second dielectric layer and a third dielectric layer located between the first dielectric layer and the second dielectric layer, and the etching rate of the third dielectric layer is greater than the etching rate of the first dielectric layer and the second dielectric layer; forming an opening at the dielectric stack layer, wherein the opening is corresponding to the pad; performing a wet etching process on the dielectric stack layer to remove the portion of the third dielectric layer surrounding the opening so as to form a gap between the portion of the first dielectric layer surrounding the opening and the portion of the second dielectric layer surrounding the opening; and performing a plating process on the dielectric stack layer and the pad to respectively form a first plating layer and a second plating layer at the dielectric stack layer and the pad, wherein the gap isolates the first plating layer from the second plating layer.
 2. The fabricating process of circuit substrate as claimed in claim 1, wherein the material of the dielectric stack layer comprises silicon oxide (SiO₂) or silicon nitride (Si₃N₄).
 3. The fabricating process of circuit substrate as claimed in claim 1, wherein the material of the first dielectric layer and the second dielectric layer comprises silicon oxide produced through a reaction in vacuum plasma by using tetraethylorthosilicate (TEOS) and the material of the third dielectric layer comprises borophosphosilicate glass (BPSG).
 4. The fabricating process of circuit substrate as claimed in claim 1, wherein the method of performing the wet etching process on the dielectric stack layer is to perform wet etching with hydrogen fluoride (HF) solution on the dielectric stack layer.
 5. The fabricating process of circuit substrate as claimed in claim 1, further comprising: prior to performing the plating process, removing a portion of the dielectric stack layer to expose the pad.
 6. The fabricating process of circuit substrate as claimed in claim 5, wherein the method of removing a part of the dielectric stack layer comprises plasma etching.
 7. The fabricating process of circuit substrate as claimed in claim 1, wherein the plating process is evaporation or sputtering.
 8. The fabricating process of circuit substrate as claimed in claim 1, further comprising: forming a patterned recess at the dielectric stack layer; and increasing the thickness of the dielectric stack layer to overlay the patterned recess, wherein after removing the portion of the third dielectric layer surrounding the opening by using the wet etching process, the dielectric stack layer forms a saw-teeth shape structure at the place of the gap.
 9. The fabricating process of circuit substrate as claimed in claim 8, wherein the method of fabricating a saw-teeth shape structure further comprises: forming a dielectric material filling the patterned recess, wherein the etching rate of the dielectric material is greater than the etching rate of the first dielectric layer and the second dielectric layer; and at the same time as performing the wet etching process to remove the portion of the third dielectric layer surrounding the opening, removing the dielectric material by using the wet etching process so that the dielectric stack layer has a saw-teeth shape structure at the place of the gap.
 10. A semiconductor process, comprising: providing a semiconductor substrate and a dielectric stack layer, wherein the semiconductor substrate has a pad, the dielectric stack layer is disposed on the semiconductor substrate and overlays the pad, the dielectric stack layer comprises a first dielectric layer, a second dielectric layer and a third dielectric layer located between the first dielectric layer and the second dielectric layer, and the etching rate of the third dielectric layer is greater than the etching rate of the first dielectric layer and the second dielectric layer; forming an opening at the dielectric stack layer, wherein the opening is corresponding to the pad; performing a wet etching process on the dielectric stack layer to remove the portion of the third dielectric layer surrounding the opening so as to form a gap between the portion of the first dielectric layer surrounding the opening and the portion of the second dielectric layer surrounding the opening; and performing a plating process on the dielectric stack layer and the pad to respectively form a first plating layer and a second plating layer at the dielectric stack layer and the pad, wherein the gap isolates the first plating layer from the second plating layer. 